Verification Methodology Manual for SystemVerilog - 9781461498131
Verification Methodology Manual for SystemVerilog Please note: this item is printed on demand and will take extra time before it can be dispatched to you (up to 20 working days). Author(s): Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale Format: Paperback Publisher: Springer-Verlag New York Inc., United States Imprint: Springer-Verlag New York Inc. ISBN-13: 9781461498131, 978-1461498131 Synopsis Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.
Specifications
| Return Postage Will Be Paid By | Buyer |
| Returns Accepted | Returns Accepted |
| After Receiving The Item, Your Buyer Should Cancel The Purchase Within | 60 days |
| Number Of Pages | 503 Pages |
| Language | English |
| Publication Year | 2014 |
| Item Height | 235 mm |
| Item Weight | 795 g |
| Type | Textbook |
| Subject Area | Electrical Engineering |
| Item Width | 155 mm |
| Format | Paperback |
What stands out about this textbook is the summary of each chapter in bullet form.
